1. Field of the Invention
The present invention relates to address allocation to word lines of a NAND flash memory.
2. Description of the Related Art
A NAND flash memory is used as a file memory and a mobile memory. In addition, recently, the NAND flash memory is used as a solid-state drive (SSD) which is a substitute for an HDD of a notebook computer. Here, the file memory is a NAND flash memory when it is incorporated alone in, for example, a memory card, a USB, and digital equipment. The mobile memory is a NAND flash memory when plural kinds of memories (such as a NOR flash memory) are combined and used, such as a multi-chip package (MCP) mounted in a cellular telephone.
In the above situations, a memory cell must be miniaturized for the purpose of increasing the memory capacity of the NAND flash memory.
However, while the size of the memory cell is reduced (shrunk), the size of a transfer transistor in a word line driver is limited by the magnitude of a write voltage, which is supplied to the word line during writing, and therefore, the size of the transfer transistor cannot be reduced, unlike the memory cell.
Therefore, at present, a transfer transistor block is comprised in such a manner that transfer transistors are arranged in an array form at one end of a memory cell array, and the word lines in one NAND block and the transfer transistor block are connected to each other through electroconductive lines (hereinafter referred to as interconnect lines) (for example, see Jpn. Pat. Appln. KOKAI Publication Nos. 7-230696, 2000-76880, 2002-141477, 2005-191413, 2005-39016, and Japanese Patent No. 3834189).
Here it is important that the layout of the transfer transistor block and the layout of the interconnect lines play a significant role in reducing the size of a chip.
Namely, those layouts have a simple repeated pattern thereby to contribute to the reduction of the chip size.